21.07.2017 - 22.07.2017 Frankfurt am Main Fachtagung / Konferenz 1520 0

Frontiers in Analog CAD

(FAC 2017)
Anmelden
Termin
Beginn: 21.07.2017
Ende: 22.07.2017
Veranstaltungs-Sprache
en-US
Veranstaltungsort

Frankfurt am Main
Goethe-Universität, Gästehaus Frauenlobstraße 1
Frauenlobstraße
60487 Frankfurt am Main

Beschreibung

Actual trends like cyber physical systems, internet of things and autonomous driving push the need for a lot of analog content on integrated circuits to connect to the physical world. Verification and design of these analog parts takes a lot of effort of the overall design process. Additionally, actual standards like ISO 26262 increase the pressure to get the verification formalized and automatized. Using current methodologies, even well- understood analog circuits require nearly as much effort to modify and/or port to a new process as the initial design. Even when an analog circuit can be reused, validating its performance within the new system – especially if the circuit is controlled through a digital loop – is often the long pole in the overall flow. The reasons for this situation are both technical and sociological; inherent differences in the behaviors of digital vs. analog systems make analog design and validation much more resistant to automation. Similarly, the cultural distance between the EDA software developers and analog designers is much larger than the distance between them and digital designers.

The goal of this workshop is to bring together technologists and researchers from analog design as well as CAD tool development to foster collaboration and exchange of ideas as well as to spur further research into the intersection of these domains. The workshop has a long tradition (since 2005) mainly in the area of formal verification.

 

Paper Presentation

The papers selected for oral presentations will be presented in 20-minute slots in the workshop program in front of an audience.
Those accepted for poster presentations will be presented in a face-to-face poster area. Poster presenters are required to prepare a short (max 5-minute) presentation for the introduction of their poster to the audience and a poster (A0 format) to support discussions. 

After the workshop, all oral and poster presentations will be posted at the official workshop website www.vde.com/FAC2017.

Veranstalter

ITG Informationstechnische Gesells. im VDE

Referenten

Program Chairs and Organization Committee
Lars Hedrich, University Frankfurt
Carna Radojicic, TU Kaiserslautern
 

Program Committee
Elad Alon, University of California
Thao Dang, CNRS/Verimag
Goran Frehse, CNRS/Verimag
Helmut Graeb, Technical Univ. of Munich
Mark Greenstreet, University of British Columbia
Christoph Grimm, TU Kaiserslautern
Chenjie Gu, Intel
Walter Hartong, Cadence
Lars Hedrich, University of Frankfurt
Kevin Jones, Plymouth University
Chandramouli Kashyap, Intel
Jaeha Kim, Seoul National University
Peng Li, Texas A&M University
Xin Li, Carnegie Mellon University
Oded Maler, Verimag, Grenoble
Jean-Paul Morin, ST Microelectronics
Chris Myers, University of Utah
Frédéric Poullet, Dolphin Integration
Carna Radojicic, TU Kaiserslautern
Sebastian Steinhorst, TU Munich
Alex Yakovlev, Newcastle University
 

Steering Committee
Mark Greenstreet, University of British Columbia
Christoph Grimm, TU Kaiserslautern
Lars Hedrich, University Frankfurt
Chandramouli Kashyap, Intel
Dejan Nikovic, AIT Vienna
Oded Maler, Verimag
Chris Myers, University of Utah
Jaeha Kim, Seoul National University
Xin Li, Duke University
Alex Yakovlev, Newcastle University
Scott Little, Mentor Graphics


Workshop History

FAC 2005
FAC 2008
FAC 2009
FAC 2011
FAC 2013
FAC 2014
FAC 2015

Bemerkungen

Final Program

Friday, July 21, 2017

09.00-09.15   Welcome
Carna Radojicic

09.15-10.00  
Keynote 1: Designing Automotive Systems in the 21th Century
Martin Barnasconi, NXP Semiconductors

10:00-10:15  
Invited Talk: Empowering Innovation, Tools and Solutions for Circuit Optimization, Sizing & Migration
Jin Qiu, MunEDA

10.15-10:45   Coffee Break

10.45-12.15   Design Robustness & Reliability
Session 1: Design Robustness & Reliability
Moderator: Lars Hedrich
 

10.45-11.15  
P1 - Towards MEMS-IC Robustness Optimization 
Florin Burcea, Andreas Herrmann, Helmut Graeb, TU Munich

11.15-11.45  
P7 -  Parasitic Symmetry at a Glance: Uncovering Mixed-Signal Constraints 
Georg Glaeser, Benjamin Saft, Ralf Sommer, IMMS

12.45-12.15   Introduction to Poster Session
Moderator: Lars Hedrich

P2 - Realistic Worst-Case for MEMS 
Andreas Herrmann, Christoph Hielscher, Alexander Mueller, Gisbert Hoelzer, Helmut Graeb, TU Munich                 
P11 - Modelling of pattern formation during electrostatic discharge 
Patrick Scharf, Christoph Sohrmann, Steffen Holland, Fraunhofer IIS/EAS
P12 - Towards Design Rules based on Structural Contracts 
Gregor Nitsche, OFFIS

12.15-13.00   Poster Session

13.00-14:00  Lunch

14.00-16.00
Session 2: Novel Techniques to Improve Verification of Mixed-Signal Designs     Novel Techniques to rov Moderator: Christoph Grimm
 

14.00-14.30  
P3 - Computer-Aided Formal Verification of Power Electronics Circuits 
Omar Beg, Luan Nquyen, Ali Davoudi, Taylor T Johnson, Vanderbuilt University

14.30-15.00  
P5 - AMS Circuit Specification Validation using Analog State Space Coverage 
Andreas Fuertig, Jochen Wagner, Lars Hedrich, University of Frankfurt

15.00-15.30  
P9 - AMT 2.0 - Monitoring Tool for Extended STL Specifications 
Oliver Lebeltel, Oded Maler, Dejan Nickovic, AIT Vienna

15:30-16:00
P8 - Model Discovery for Analog/Mixed-Signal Circuits 
Vladimir Dubikhin, Chris Myers, Alex Yakovlev, Daniel Sokolov, Andrey Mokhov, Newcastle University

19.00-23.30  Social event
 

Saturday, July 22, 2017

09:00-09:15   Welcome

09:15-10:30   
Session 2: Novel Techniques to Improve Verification of Mixed-Signal Designs
Moderator: Chris Myers

09.15-10.00  
Keynote 2: Bordersearch: An Adaptive Identification of Failure Regions
Monica Rafaila, OneSpin Solutions

10.00-10.30  
P6 - Affine Arithmetic Decision Diagrams for Mixed-Signal Verification

Carna Radojicic, Christoph Grimm, TU Kaiserslautern

10.30-11.00   Coffee break

11.00-12.00
Session 3: Recent Advances in Mixed-Signal Simulation   Recent Advances in Mixed-Signal Simulation
Moderator: Dejan Nickovic
 

11.00-11.30  
P4 - Accelarated Mixed-Signal Simulations Using Multi-Core Architecture
Sara Divanbeigi, Evan Aditya, Markus Olbrich, Leibniz Univ. Hannover

11.30-12.00  
P10 - Dynamic Simulation of Power Consumption for Model Based Design of Mixed-Signal Systems

Xiao Pan, Christoph Grimm, TU Kaiserslautern

12.00-13.00   Lunch

13.00             End of event
 


 

 

Kontakte

Contact
Carna Radojicic
Technische Universität Kaiserslautern
Gottlieb-Daimler Strasse 49
67663 Kaiserslautern

8ru50ztztQt9.@4z-12.uv Tel. +49 631 2052606

Prof. Dr.-Ing. Lars Hedrich
University of Frankfurt
Robert-Mayer-Str. 11-15
60325 Frankfurt

yvu8ztyQv3.t9.@4z-w8r41w@8_.uv Tel. +49 69 798 22297

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